Shallow trench isolation structure for shielding trapped charge in a semiconductor device

ABSTRACT

A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D 1  and is above the second plane by a second distance D 2  that is less than D 1 .

This application is a continuation application claiming priority to Ser.No. 11/276,132, filed Feb. 25, 2006.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a structure and method to shield atrapped charge from devices within a semiconductor structure.

2. Related Art

Unwanted electrical charges within an electrical structure may causedevices within the electrical structure to malfunction. Therefore thereis a need for protecting devices within an electrical structure from theaffects of unwanted electrical charges.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor structure, comprising:

a first field effect transistor (FET) comprising a channel region formedfrom a portion of a silicon substrate, a source structure formedadjacent to said channel region, a drain structure formed adjacent tosaid channel region, a gate dielectric formed over said channel region,and a gate electrode formed over said gate dielectric, wherein a bottomsurface of said gate electrode is in direct physical contact with saidgate dielectric, wherein said channel region comprises a first cornerdevice and a second corner device, wherein a top surface of said channelregion is located within a first plane, and wherein said bottom surfaceof said gate electrode is located within a second plane;

a second FET; and

a shallow trench isolation (STI) structure located adjacent to saidchannel region, wherein said STI structure isolates said first FET fromsaid second FET, wherein said STI structure comprises a dielectric linerformed in a trench within said silicon substrate, a conductive STI fillstructure formed over said dielectric layer, and a dielectric cap layerformed over and in contact with a top surface of said conductive STIfill structure, wherein said top surface of said conductive STI fillstructure is above said first plane by a first distance D₁ and is abovesaid second plane by a second distance D₂ that is less than D₁.

The present invention provides method for forming a semiconductorstructure, comprising:

providing a silicon substrate;

forming, within said a silicon substrate, a shallow trench isolation(STI) structure comprising a dielectric liner formed in a trench withinsaid silicon substrate, a conductive STI fill structure formed over saiddielectric layer, and a dielectric cap layer formed over and in contactwith a top surface of said conductive STI fill structure;

forming within said bulk silicon substrate, a first field effecttransistor (FET) and a second FET, wherein said first FET comprises achannel region formed from a portion of said silicon substrate, a sourcestructure formed adjacent to said channel region, a drain structureformed adjacent to said channel region, a gate dielectric formed oversaid channel region, and a gate electrode formed over said gatedielectric, wherein a bottom surface of said gate electrode is in directphysical contact with said gate dielectric, wherein said channel regioncomprises a first corner device and a second corner device, wherein atop surface of said channel region is located within a first plane,wherein said bottom surface of said gate electrode is located within asecond plane, wherein said shallow trench isolation (STI) structurelocated adjacent to said channel region, wherein said STI structureisolates said first FET from said second FET, wherein said top surfaceof said conductive STI fill structure is above said first plane by afirst distance D₁ and is above said second plane by a second distance D₂that is less than D₁.

The present invention advantageously provides a system and associatedmethod for protecting devices within an electrical structure from theaffects of unwanted electrical charges.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a perspective view of a semiconductor structure 2comprising a shallow trench isolation (STI) structure, in accordancewith embodiments of the present invention.

FIG. 2 illustrates a first cross sectional view of the semiconductorstructure of FIG. 1, in accordance with embodiments of the presentinvention.

FIG. 3 illustrates an alternative to the semiconductor structure 2 ofFIG. 2, in accordance with embodiments of the present invention.

FIG. 4 illustrates a second cross sectional view of the semiconductorstructure of FIG. 1, in accordance with embodiments of the presentinvention.

FIG. 5A-5F illustrate a cross sectional view of a forming method andstructure for forming a semiconductor structure of FIGS. 1 and 2, inaccordance with embodiments of the present invention.

FIG. 6 illustrates a flowchart describing a process for forming thesemiconductor device of FIGS. 1-5, in accordance with embodiments of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a perspective view of a semiconductor structure 2comprising a shallow trench isolation (STI) structure 11, in accordancewith embodiments of the present invention. The semiconductor structure 2comprises a silicon substrate 10, a field effect transistor (FET) 21, aFET 23 (only partially shown in FIG. 1), and the STI structure 11 (i.e.,comprising a dielectric liner 36, a conductive STI fill structure 32,and a dielectric cap structure 34). The STI structure 11 is locatedwithin a trench (i.e., see trench 40 in FIG. 5B) formed in the siliconsubstrate 10 between the FET 21 and the FET 23. The STI structure 11physically and electrically isolates the FET 21 from the FET 23. Thefollowing description of FET 21 also applies to FET 23. The FET 21comprises a source structure 48 a, a drain structure 48 b, a gatedielectric layer 14, a shared gate electrode 16 (i.e., the gateelectrode 16 is shared by the FET 21 and the FET 23), and a channelregion 24. The channel region 24 is formed from a portion of the siliconsubstrate 10 and is located between the source structure 48 a and thedrain structure 48 b. The channel region 24 provides a conductive path(i.e., controlled by the gate electrode 16) between the source structure48 a and the drain structure 48 b. The channel region 24 comprisescorner devices 22. The corner devices 22 are defined as edge sections ofthe channel region 24. The corner devices 22 are parasitic devicescomprising slightly different physical and electrical characteristicsthan a central portion 19 of the channel region 24.

Semiconductor structures (e.g., semiconductor structure 2) may be used(operated) in any type of circuitry. During operation of semiconductorstructures over a period of time, an unwanted electrical charge buildup26 (see FIG. 2) in dielectric regions of STI structure may be causedwhen operating the semiconductor structure within circuits in certainenvironments. For example, when a semiconductor structure is operatedover a period of time in circuitry within a radiation environment (e.g.,satellite circuitry, circuitry in a nuclear power plant, etc.),radiation (e.g., from a solar burst, from nuclear power plantfacilities, etc) may cause a trapped electrical charge build up to formwithin dielectric regions of STI structure within the semiconductordevice. If the dielectric regions of the STI structure are located nearFET channel regions (e.g., channel region 24), the trapped electricalcharge build up in the STI structure may cause corner devices (e.g.,corner devices 22) to turn on thereby increasing source to drain leakagecurrents which in turn may cause the semiconductor structure (i.e., theFETS within the semiconductor structure) to malfunction and ultimatelyfail. Therefore, the semiconductor structure 2 of FIG. 1 provides an STIstructure 11 that shields the corner devices 22 within the channelregion 24 from any an unwanted electrical charge buildup within the STIstructure 11 (i.e., within the dielectric cap structure 34).

The STI structure 11 of FIG. 1 comprises a dielectric liner 36, aconductive STI fill structure 32, and a dielectric cap structure 34. Thedielectric liner 36 lines a formed trench (e.g., see trench 40 in FIG.5B) and the conductive STI fill structure 32 is formed over and incontact with the dielectric liner 36. The dielectric cap structure 34 isformed over a top surface 31 of the conductive STI fill structure 32.The dielectric liner 36 and the dielectric cap structure 34 maycomprise, inter alia, silicon dioxide. The conductive STI fill structure32 may comprise, inter alia, doped polysilicon. The dielectric liner 36may comprise a thickness T₁ of about 2 nanometers (nm) to about 20 nm.The dielectric cap structure 34 may comprise a thickness T₂ of about 20nm to about 100 nm. A top surface 20 of the channel region 24 resides ina first plane. During operation (i.e., over a period of time) of the ofthe semiconductor structure 2 in certain environments (e.g., a radiationenvironment such as, inter alia, satellite circuitry, circuitry in anuclear power plant, etc.), an unwanted electrical charge buildup 26(i.e., see FIG. 2) may be found within the dielectric cap structure 34.No such charge buildup is possible in conductive materials, such as thatemployed for the conductive STI fill structure 32. If the electricalcharge buildup 26 within the dielectric cap structure 34 occurs near thechannel region 24, the electrical charge buildup 26 could cause thecorner devices 22 to turn on thereby increasing source structure 48 a todrain structure 48 b leakage currents which in turn may cause thesemiconductor structure 2 (i.e., the FETS 21 and 23) to malfunction andultimately fail. Therefore, the STI structure 11 is formed such that thetop surface 31 of the conductive STI fill structure 32 is raised aspecified distance (D₁) above (i.e., with respect to direction 7) thefirst plane. As a result of the above mentioned configuration (i.e., theraised top surface 31), the dielectric cap structure 34 (i.e., formed onthe top surface 31 of the conductive STI fill structure 32) is alsoraised above the first plane so that the dielectric cap structure 34 isnot adjacent to the channel region 24. The conductive STI fill structure32 shields the corner devices 22 from any electrical charge 26 buildupwithin the dielectric cap structure 34 thereby preventing damage to theFETS 21 and 23. The top surface 31 of the conductive STI fill structureextends above first plane (and the top surface 20 of the channel region24) by a distance D₁ that is about 1.5 to about 4 times the thickness T₁of the dielectric liner 36. The distance D₁ may be selected from a rangeof about 5 nanometers to about 80 nm nanometers.

FIG. 2 illustrates a first cross sectional view of the semiconductorstructure 2 of FIG. 1, in accordance with embodiments of the presentinvention. The first cross sectional view of FIG. 2 is taken along line2-2 of FIG. 1. FIG. 2 clearly illustrates the distance D₁ (i.e., asdescribed in the description of FIG. 1) and the unwanted charge build up26 within the dielectric cap structure 34. Additionally, FIG. 2illustrates a distance D₂. The distance D₂ represents a distance thatthe top surface 31 of the conductive STI fill structure 32 is raisedabove (i.e., with respect to direction 7) a second plane (i.e., a bottomsurface 23 of the gate electrode 16 resides in the second plane). Thedistance D₁ is greater than the distance D₂.

FIG. 3 illustrates an alternative to the semiconductor structure 2 ofFIG. 2, in accordance with embodiments of the present invention. Incontrast to the semiconductor structure 2 of FIG. 2, the semiconductorstructure 2 a of FIG. 3 comprises electrical connections 82 between theconductive STI fill structure 32 and the silicon substrate 10. A portionof the dielectric liner 36 has been removed prior to formation ofconductive STI fill structure 32 so that the conductive STI fillstructure 32 may be electrically connected to the silicon substrate 10.The electrical connections 82 will prevent electrical floating of theconductive STI fill structure 32 without necessitating any additionaltop-side connections.

FIG. 4 illustrates a second cross sectional view of the semiconductorstructure 2 of FIG. 1, in accordance with embodiments of the presentinvention. The second cross sectional view of FIG. 2 is taken along line4-4 of FIG. 1.

FIG. 5A-5F illustrate a cross sectional view of a forming method andstructure for forming a semiconductor structure 2 of FIGS. 1 and 2, inaccordance with embodiments of the present invention.

FIG. 5A illustrates the silicon substrate 10 comprising a pad structure42, in accordance with embodiments of the present invention. The padstructure 42 may comprise, inter alia, a pad oxide layer and a padnitride layer. Portion 10 a of the silicon substrate 10 and portion 42 aof the pad structure 42 comprise portions that will be removed in orderto form the shallow isolation trenches 40 of FIG. 5B.

FIG. 5B illustrates a formed shallow trench 40 within the siliconsubstrate 10, in accordance with embodiments of the present invention. Amasking/etching process is used to form the shallow isolation trenches40. Any masking/etching process using standard lithographic techniquesknown to a person of ordinary skill in the art may be used. Themasking/etching process removes the portion 42 a (i.e., from FIG. 5A) ofthe pad structure 42 and portion 10 a (i.e., from FIG. 5A) of thesilicon substrate 10. The pad structure 42 may be processed to athickness T₃ such that after a planarization process, the conductive STIfill structure 32 will be above a top surface 43 of the siliconsubstrate 10 by a minimum amount. Note that surface 43 of the siliconsubstrate 10 will become surface 20 of the channel region 24.

FIG. 5C illustrates a formation of the dielectric liner 36, inaccordance with embodiments of the present invention. The shallowisolation trenches 40 are lined with the dielectric liner 36. Thedielectric liner 36 may comprise, inter alia, silicon dioxide. Thedielectric liner 36 may be formed as a thermally-grown silicon dioxide,using a chemical vapor deposition (CVD) process to deposited silicondioxide, or any combination thereof. The dielectric liner 36 may beformed comprising a thickness of about 3 nm to about 20 mm.

FIG. 5D illustrates a formation of the conductive STI fill structure 32,in accordance with embodiments of the present invention. The conductiveSTI fill structure 32 is formed within the remaining portion of theshallow isolation trench 40 (i.e., after the dielectric liner 36 hasbeen formed). Material for conductive the STI fill structure 32 (e.g.,doped polysilicon) is deposited over the entire structure, thenplanarized to the top of pad structure 42, using a known process suchas, inter alia, chemical-mechanical polishing, etc. A recess 63 is thenformed within the conductive STI fill structure 32 such that the surface31 of the conductive STI fill structure 32 extends above the top surface20 of the channel region 24 (i.e., within the silicon substrate 10) bythe distance D₁ that is about 1.5 to about 4 times the thickness T₁ ofthe thin dielectric liner 36.

FIG. 5E illustrates a first formation step for forming the dielectriccap structure 34 of FIGS. 1 and 2, in accordance with embodiments of thepresent invention. A cap dielectric layer 60 is formed within the recess63 (see FIG. 5D) and over a top surface 68 of the pad structure 42. Thecap dielectric layer 60 may comprise, inter alia, silicon dioxide. Thecap dielectric layer 60 may be formed using any technique known to aperson of ordinary skill in the art including, inter alia, a CVDprocess.

FIG. 5F illustrates a second formation step for forming the dielectriccap structure 34 of FIGS. 1 and 2, in accordance with embodiments of thepresent invention. A portion of the cap dielectric layer 60 is removedand the resulting dielectric cap structure 34 is planerized such that atop surface 70 of the dielectric cap structure 34 is coplanar with thetop surface 68 of the pad structure 42.

FIG. 5G illustrates a formation of a recess 79, in accordance withembodiments of the present invention. The recess 79 is formed byremoving the pad structure 42. After the pad structure 42 is removed thesemiconductor structure 2 of FIGS. 1 and 2 is formed by forming the,implanted wells, the gate dielectric 14 layer, the gate electrode 16,the source structure 48 a and the drain structure 48 b in accordancewith techniques known to a person of ordinary skill in the art. Anadditional over-etch during patterning of the gate electrode 16 will berequired to clear the extra topography introduced by having the stepbetween the top surface 20 of channel region 24 and the top surface ofthe dielectric cap structure 34.

FIG. 6 illustrates a flowchart describing a process for forming thesemiconductor device of FIGS. 1-5, in accordance with embodiments of thepresent invention. In step 100, the pad structure 42 is formed. In step102, a masking/etching process is used to form the shallow isolationtrenches 40. Any masking/etching process using standard lithographictechniques known to a person of ordinary skill in the art may be used.In step 104, the shallow isolation trenches 40 are lined with thedielectric liner 36. In optional step 106, portions of the dielectricliner 36 are optionally removed so that the semiconductor structure 2 aof FIG. 3 comprising the electrical connections 82 between theconductive STI fill structure 32 and the silicon substrate 10 may beformed. The portions of the dielectric liner 36 may be removed using,inter alia, an RIE process. In step 108, the conductive STI fillstructure 32 is formed within the remaining portion of the shallowisolation trench 40 (i.e., after the dielectric liner 36 has beenformed). In step 110, A recess 63 is formed within the conductive STIfill structure such that the surface 31 of the conductive STI fillstructure 32 extends above the top surface 20 of the channel region 24(i.e., within the silicon substrate 10) by the distance D that is about1.5 to about 4 times the thickness T₁ of the dielectric liner 36. Instep 112, the dielectric cap structure 34 is formed. In step 114, thepad structure 42 is removed. In step 116, the implanted wells, the gatedielectric 14 layer and the gate electrode 16 are formed in accordancewith techniques known to a person of ordinary skill in the art. In step118, the FET 21 is formed in accordance with techniques known to aperson of ordinary skill in the art.

While embodiments of the present invention have been described hereinfor purposes of illustration, many modifications and changes will becomeapparent to those skilled in the art. Accordingly, the appended claimsare intended to encompass all such modifications and changes as fallwithin the true spirit and scope of this invention.

1. A semiconductor structure, comprising: a first field effecttransistor (FET) comprising a channel region formed from a portion of asilicon substrate, a source structure formed adjacent to said channelregion, a drain structure formed adjacent to said channel region, a gatedielectric formed over said channel region, and a gate electrode formedover said gate dielectric, wherein a bottom surface of said gateelectrode is in direct physical contact with said gate dielectric,wherein said channel region comprises a first corner device and a secondcorner device, wherein a top surface of said channel region is locatedwithin a first plane, and wherein said bottom surface of said gateelectrode is located within a second plane; a second FET; and a shallowtrench isolation (STI) structure located adjacent to and in contact withsaid channel region, wherein said STI structure isolates said first FETfrom said second FET, wherein said STI structure comprises a dielectricliner formed in a trench within said silicon substrate, a conductive STIfill structure formed over said dielectric layer, and a dielectric caplayer formed over and in contact with a top surface of said conductiveSTI fill structure, wherein said top surface of said conductive STI fillstructure is above said first plane by a first distance D₁ and is abovesaid second plane by a second distance D₂ that is less than D₁, andwherein said gate dielectric is formed over and in contact with saiddielectric cap layer of said STI structure.
 2. The semiconductorstructure of claim 1, wherein said STI structure is adapted to shieldsaid first corner device and said second corner device from a trappedelectrical charge build up within said dielectric cap layer, and whereinsaid electrical charge build up within said dielectric cap layer isgenerated during operation of said first FET and said second FET over aperiod of time.
 3. The semiconductor structure of claim 1, wherein saidconductive STI fill structure comprises doped polysilicon.
 4. Thesemiconductor structure of claim 1, wherein each of said dielectricliner and said dielectric cap layer comprise silicon dioxide.
 5. Thesemiconductor structure of claim 1, wherein said first distance D₁ isconfigured to prevent a trapped electrical charge build up within saiddielectric cap layer from electrically damaging said first corner deviceand said second corner device.
 6. The semiconductor structure of claim1, wherein said dielectric liner comprises a thickness T configured toprevent trapped electrical charge build up within said dielectric linerfrom electrically damaging said first corner device and said secondcorner device.
 7. The semiconductor structure of claim 6, wherein saidthickness T is in a range of about 2 nanometers to about 20 nanometers.8. The semiconductor structure of claim 1, wherein said dielectric linercomprises a thickness T, and wherein said distance D₁ is in a range ofabout 1.5*T to about 4*T.
 9. The semiconductor structure of claim 8,wherein said distance D₁ is in a range of about 5 nanometers to about 80nanometers.
 10. The semiconductor structure of claim 1, wherein a bottomsurface of said conductive STI fill structure is electrically connectedto said silicon substrate.
 11. The semiconductor structure of claim 1,wherein said gate electrode is formed over said dielectric cap layer ofsaid STI structure.
 12. The semiconductor structure of claim 1, whereinsaid dielectric liner is formed in said trench such that said conductiveSTI fill structure is not in contact with said silicon substrate. 13.The semiconductor structure of claim 1, wherein said second FETcomprises a second channel region formed from a second portion of saidsilicon substrate, and wherein said shallow trench isolation (STI)structure is located adjacent to and in contact with said second channelregion.